The disclosure relates to the field of electronic design automation (EDA). More particularly, the disclosure relates to the field of power modeling used in EDA tools.
In integrated circuit (IC) design flow, designers use EDA tools to implement their ideas into a physical circuit. An ASIC design flow is shown in FIG. 1. Circuit designers can use EDA tools to start from behavior-level 102, to gate-level 104, then to transistor-level 106. In behavior-level 102, the idea is represented by Boolean functions. After synthesizing by EDA tool, the idea in behavior-level could turn into gate-level netlist. In gate-level 104, the netlist is represented by logic gates. After placement and routing, the gate-level netlist is converted to a transistor-level circuit. In transistor-level 106, the circuit is represented by transistors and the connections thereof.
Along with the design conversion from behavior-level to transistor-level, the EDA tools also estimate circuit performance at the behavior and gate-level, such as timing, area, power consumption, etc. Only when the estimated results at behavior-level 108 meets the design specification, can designers can move on to the next level. Similarly, designs are allowed to be operated in transistor-level process when the gate-level estimation can meet its design specification. Since the results 108 and 110 are only estimated results, the measured value 112 after physical implementation may not met the design specifications. If the measured value 112 at the transistor-level fails to meet the design specification or customer requirements, for example, the measured value 112 is too large on area, processing of a testbench is too time consuming, or too much power consumption, the designer must re-design the circuit from the behavior level stage. To reduce development time, designing a precise estimation tool is required aid in evaluating circuit performance at the behavior-level and gate-level.
FIG. 2 is a prototype of a random access memory (RAM) device 200 showing address port ADDR, data port DATA, write enable pin WEN, and chip enable pin CEN. When a RAM operates in idle modes, the chip enable pin CEN should be logic 1. When a RAM operates in a read mode, the chip enable pin CEN should be logic 0 and the write enable pin should be logic 1. As a RAM operates at write mode, the chip enable pin CEN and the write enable pin WEN should be logic 0.
FIG. 3 shows a TSMC 0.25μm Process SRAM Generator User Manual by Artisan (2002). In FIG. 3, the memory power model is built according to operating modes. The operating modes are idle mode 302, read mode 304, and write mode 306. The operating mode can be determined based on the WHEN statement. FIG. 4 shows a power model of a synchronous RAM from U.S. Pat. Nos. 5,838,579 and 6,480,815. In FIG. 4, the memory power model is also built by operating modes. The operating modes are idle mode 402, read mode 404. and write mode 406. The operating mode can be determined based on the WHEN statement.
An EDA tool can count the numbers of operating modes and lookup its corresponding power table to calculate the power consumption of a memory device. FIG. 5 shows an average current curve versus clock cycle. When a memory device operates at 10 MHZ, write mode 502 and read mode 504, the average difference in current is 100 μA. It seems reasonable to build the memory power models by operating modes. In fact, building a power model by just separating their operation modes are not precise enough, because even in the same operating mode may exist an un-neglect gap, for example, write mode 502, the current consumed varies from 640 μA to almost 730 μA. This implies that if the memory power model similar to that on FIG. 3 or FIG. 4 is used, the results of estimating power consumption would be too pessimistic or too optimistic.